Semiconductor devices, such as memory devices, use field effect transistors (FETs) to create the integrated circuits required during the fabrication of complimentary metal oxide semiconductor (CMOS) devices on a semiconductor wafer or other substrate. The fabrication of CMOS devices require advanced isolation techniques to create isolation between neighboring FETs.
One conventional isolation technique known as shallow trench isolation (STI) is used where a trench is etched into a silicon substrate and the trench is filled with an oxide insulator material and planarized. The STI then functions as isolation between subsequently formed FETs and provides many desirable circuit device properties.
However, the current STI techniques also possess some disadvantages. For example, FIG. 1 depicts a current STI dry etch process used to fabricate a flash device. FIG. 1 shows array section 10 and periphery section 11 on substrate 12. In array section 10, trenches 13 have been etched into substrate 12 and in periphery section 11, trenches 14 have been etched into substrate 12. At this point, the current technique is to form a mask over array section 10 and a subsequent etch step is performed on periphery section 11 to increase the depth of trenches 14. In this example, the resulting depth Δ between the depth of array trenches 12 and periphery trenches 14 is only approximately 380 Å and as indicated, to create the depth Δ between trenches 12 and 14 an additional mask step and etch step are required that increase production cost of the device and possibly limit the electrical properties of the device.
Accordingly, STI formation techniques are needed that will improve the electrical property of CMOS devices and also reduce production costs.